1. Field of the Invention
The present invention relates to DDR memory devices. More particularly, the present invention relates to read data stage circuitry architecture for Mobile DDR memory device controllers.
2. The Prior Art
DDR-SDRAM devices can transfer data twice as fast as regular SDRAM chips (SDR-SDRAM). This is because DDR-SDRAM devices can send and receive signals twice per clock cycle. Mobile DDR-SRAM devices are a kind of DDR memory device designed for low-power consumption. Their intrinsic timings for read accesses slightly differs from that of standard DDR memory devices.
FIG. 1 is a block diagram that shows a typical microcontroller system architecture 10 employing a microprocessor 12 connected to a DDR-SDRAM device 14. Conventional Crystal oscillators can generate frequencies up to 30 MHz. To obtain clock frequencies of 100 Mhz and higher for use by the microprocessor 12 and the system bus, there is a need to employ phase-locked loop (PLL) circuitry. The system clock may be generated from the main oscillator and PLL 16 that can be found in a microprocessor circuit. The main oscillator and PLL circuitry 16 is used to multiply the frequency produced by the crystal oscillator. If the microprocessor circuit 12 drives a DDR memory device 14, a DDR-SDRAM memory controller 18 must be used and this module requires DQS-delay circuitry 20 to delay DQS signals 22 and 24 from DDR-SDRAM memory for read operations.
If the system bus (26, 28, and 30) and microprocessor 12 (also known as CPU) are clocked at 100 MHz, then any write access to DDR memory controller 18 will require the PLL 16 to be configured at 200 MHz for the DDR-SDRAM controller 18 to align the data with the waveforms shown in FIG. 3. This may be performed by logic within the DDR-SDRAM controller 18 that is clocked at 2× frequency of the main clock frequency of the DDR-SDRAM controller 18.
In order to drive the microprocessor 12 and system bus (26, 28, and 30) and main logic of the DDR-SDRAM controller module at 100 MHz, a divide-by-2 circuit 32 is used to derive the 100 MHz system clock 34 from the 200 MHz PLL output. This clock is gated and supplied to the DDR-SDRAM memory device 14 on clock line 36.
The DDR-SDRAM controller 18 drives the DDR-SDRAM memory device 14 through buffers 38. The propagation delay for each buffer is assumed to be the same for simplicity purposes. In real-life the delay for each buffer may be slightly different but without significant difference because buffers are high-drive buffers designed to drive DDR devices and share roughly the same capacitive load. The command signals 40 (RAS/CAS/WE/CKE) passed to the DDR-SDRAM device 14 must be aligned in such a way that a setup time and hold time is guaranteed with respect to the rising edge of the clock signal provided to the memory device on clock line 36.
For each type of memory the read data bus 42 must be properly sampled and the data must be passed to the system bus (shown as rdata 30 in FIG. 1). For proper operation, the edge of the DQS signal is delayed so that sampling occurs in the middle of the data window. Read logic 44 drives read registers 46 to accomplish this task.
Referring now to FIG. 2, a block diagram illustrates the details of an arrangement of read registers 46 that may be used to properly sample the output data from the DDR-SDRAM device 14. As is shown in FIG. 2 several internal registers are required to pass data onto the system bus. The first set of registers 48 (DataReg1) captures data D0, the second set of registers 50 (DataReg2) captures data D1. When the rising edge of the system bus clock on line 52 occurs somewhere in the window period of captured data D1, the data capture register 50 holding D1 is ready but the data capture register 48 holding D0 may no longer be holding D0 depending on the propagation delay (T1). If T1 is very low, then this capture register 48 may have already switched to the D2 value and therefore cannot provide the system bus with D0 and D1. Therefore another capture register 54 (DataReg3) samples the data captured by register 48 for each falling edge of the delayed DQS signal, using inverter 56 to invert the delayed DQS signal on line 58.
At the rising edge of the CPU clock the 32-bit data is formed by sampling both 16-bit data capture registers 50 and 54. If the propagation delay in the I/O pad providing data and clock to the DDR-SDRAM device 14 varies from 0 to half the period of the DDR clock/CPU clock, the data sampled will be correct. The data sampling circuitry is safe and robust. When read accesses are performed, data from the DDR-SDRAM device 14 must be sampled but when no access is being performed it may be useful to prevent data switching by holding the data provided to the system bus to achieve lower power consumption. This is done by providing sample-and-hold functions which consist of DFFs 60 and 62 and multiplexers 64 and 66. One input of each multiplexer recirculates the data output of the DFF to its D input. When a multi-bit signal has to be stored, this architecture is repeated for each bit of the multibit signal.
FIG. 3 illustrates the best and worst case timings (shown as T1=min and T1=max, respectively) for read accesses for a standard DDR-SDRAM memory device at a frequency of 100 MHz for a given manufacturing process, operating voltage and temperature (PVT). Both values of T1 are shorter than one-half the clock period of the DDR clock. The circuit of FIG. 2 accommodates the worst-case timing shown in FIG. 3.
FIG. 4 illustrates the best and worst-case timings for read accesses for a mobile DDR-SDRAM device at a frequency of 100 MHz for a given PVT. Compared to the timing of the standard DDR-SDRAM shown in FIG. 3, the best and worst case timings (Tacc_min and Tacc_max) for the mobile DDR-SDRAM have a larger dispersion as may be seen in FIG. 4 and are shown separately. It is seen that, at some higher frequencies, the value Tacc_max may be larger than one-half of the clock period of the DDR clock depending on the clock frequency used to clock the DDR memory device. When standard and mobile DDR-SDRAM devices may be used with a microcontroller, the user may not want to reduce the frequency of the system clock to accommodate the different memory device types. In order to obtain proper operation, the intrinsic timing differences must be accommodated at higher clock frequencies to avoid data-read errors.
Because mobile DDR-SDRAM memory devices have a large variation in propagation delay (access time), the difference in best case and worst case access time is greater than half the CPU clock period/clock sent to the DDR memory device for some range of frequencies. If it is desired to drive mobile DDR memory devices at the same CPU clock frequency used to drive standard DDR memory devices using the read data stage of FIG. 2, unpredictable behavior of read data stage circuitry may result in which it will work properly with worst-case timing but will not operate properly with best-case timing. In between best-case and worst-case timing, it is not possible to predict the point at which the circuit 46 will switch from working to non-working.
FIG. 5 is a set of timing diagrams that illustrate the operation of the circuit of FIG. 2 for a standard DDR-SDRAM memory device under best-case and worst-case timing conditions. As shown in FIG. 5, the sampling point occurs when the data in registers 50 (DataReg2), and 54 (DataReg3) is valid. The delay T1 represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line 36 of FIG. 1 and the external clock signal input CLK to the DDR memory in FIG. 1. Delay T2 represents the delay between the edge of the DDR CLK signal to the DDR-SDRAM memory device of FIG. 1 and the delayed DQS signal from DQS delay circuit 20 of FIG. 1. T3 is the register 50 hold time. Under both the best-case and worst-case conditions, the D0 and D1 data is stable in the capture DFFs DataReg2 and DataReg3 and thus is correctly transferred to the system bus by the sampling DFFs.
FIG. 6 is a set of timing diagrams that illustrate the operation of the circuit of FIG. 2 for a mobile DDR-SDRAM memory device under worst-case conditions. FIG. 6 shows the relevant waveforms when the access time of the mobile DDR memory device is very high (7 ns), which is more than half the clock period of 5 ns. This is the worst-case access time and is essentially equivalent to the worst-case access time of a standard DDR memory device. The delay T1 represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line 36 of FIG. 1 and the external clock signal input CLK to the DDR memory in FIG. 1. Delay T2 represents the delay between the edge of the external DDR CLK signal to the DDR-SDRAM memory device of FIG. 1 and the delayed DQS signal from DQS delay circuit 20 of FIG. 1 that occurs after the access time of the DDR-SDRAM memory device. T3 is the captured data setup time compared to the rising edge of system bus clock.
It may be seen that the basic read stage circuitry 46 of FIG. 2 behaves correctly under the timing conditions of FIG. 6. The delay T3 is greater than the setup time for a DFF or other sequential element used to capture data that will be sampled onto the system bus. As shown in FIG. 6, at the end of delay T3, the D0 and D1 data respectively stored in DataReg3 and DataReg2 is stable in the capture DFFs and thus is correctly transferred to the system bus by the sampling DFFs.
There is range of operating conditions where the circuit behavior will be unpredictable. This is shown with reference to FIG. 7, a set of timing diagrams that illustrate the operation of the circuit of FIG. 2 for a mobile DDR-SDRAM memory device under best-case conditions. FIG. 7 shows the relevant waveforms when the access time of the mobile DDR memory device is very low (2 ns), which is less than half the clock period (5 ns). Again, the delay T1 represents the buffer delay between the internal RAS/CAS/WE/Cke signals and those signals at the external pads as well as the buffer delay between the edge of the gated clock signal at line 36 of FIG. 1 and the external clock signal input CLK to the DDR memory in FIG. 1. Delay T2 represents the delay between the edge of the external DDR CLK signal to the DDR-SDRAM memory device of FIG. 1 and the delayed DQS signal from DQS delay circuit 20 of FIG. 1 that occurs after the access time of the DDR-SDRAM memory device. It will appear obvious to those skilled in the art that if T1 and the access time are very low, then data D0 and D1 will be respectively stored in DataReg3 and DataReg2 one clock cycle before the sampling point of the system bus.
Consider the DDR memory device access time constant. If the system frequency is increased, the conditions shown in FIG. 7 will exist. If the system frequency is reduced, the conditions shown in FIG. 6 will exist. While T3 is positive (i.e., greater than the DFF setup time plus the propagation delay of combinational logic that would be placed prior to drive the D input of the DFF) there is no problem. If, however, T3 is less than this value or negative as shown in FIG. 7, there is a problem. As a consequence, if the access time varies due to operating condition changes (temperature, voltage, etc.) then either a range of temperature and/or range of voltage will be forbidden or, for a given operating conditions, a clock frequency range will be forbidden. T3 is a consequence of T2 and the system clock period. Therefore such read data stage circuitry cannot be used for mobile DDR-SDRAM memory devices at some frequencies.
Consider the system clock frequency to be constant. If the DDR memory device access time plus the time T1 is increased, the conditions shown in FIG. 7 will exist. If the DDR memory device access time is reduced, the conditions shown in FIG. 6 will exist. While the DDR memory device access time plus the propagation delay of combinational logic that would be placed prior to drive the D input of the DFF plus the DFF setup time is greater than the system clock period there is no problem. On the contrary as shown in FIG. 6, there is a problem. As a consequence, if the access time varies due to operating condition changes (temperature, voltage, etc.), then either a range of temperature and/or range of voltage will be forbidden or, for given operating conditions, a range of access time will be forbidden. Therefore such read data stage circuitry cannot be used for mobile DDR-SDRAM memory devices under different operating conditions.